But concurrent or out-of-order execution kind of imply pipelining - you need to fill the pipeline with not just the current instruction, but also one or more following instructions to be able to deduce if you can run them concurrently.

Pipelining is basically the first trembling step towards a superscalar solution.

Todays cost of transistors makes it quite easy to build advanced pipelines, and to fill the processor with multiple identical processing units. It is also easy to make a wide flash interface, allowing multiple instructions to be fetched into the pipeline at the same time.

Almost all existing processors has a pipeline - if nothing else, it at the very least allows the prefetch of the next instruction while saving the just produced result.

The alternative to a pipeline is basically the original 12-clock 8051, where you have the states S1 to S6. Everything has a reserved time slot for simplicity, but large parts of the processor always idling because of the lack of concurrency. For most op-codes, the 12-clocker does extra op-code fetches that gets directly discarded.