| ??? 05/15/09 06:59 Read: times |
#165366 - Are we talking about the same thing? Responding to: ???'s previous message |
Richard Erlacher said:
It's still predictable, since computer programs can and will "know" exactly what the state of the pipeline is, in the event that the core is pipelined. Never contested. Just noted that a pipeline has a startup time. Richard said:
I disagree with the notion that the 805x ALU is small, as compared with the remainder of the logic. Please stop extrapolating. I did write "The ALU etc of the 8051 are so tiny that it is very easy for the pipeline to compute both sides of a conditional branch, and throw away the wrong alternative." Don't know where you thought you saw "compared with the remainder of the logic". The ALU of a 8051 is small, if you compare it with the ALU of more recent processors. If bigger processors can manage to compute both sides of a conditional branch, then it must obviously be possible to do for a 8051 chip too. The reason? To run a pipeline at fixed speed without worrying about any pipe stall if the chip mispredicts the branch decision. It is also quite common to separate address calculations from the general ALU, so having two ALU does not mean having two identical copies of what the original 8051 had. The user is interested in the hehaviour, not what building block a specific transistor is located in. Richard said:
Yes, you're right ... the logic depth, which can be fairly well equalized, using short, wide paths rather than narrow long ones, will provide the rate-determining step. However, if a 3-byte instruction, e.g. MOV A,#HHHH takes just as long as a single-byte instruction, MOV B,A, or a two-byte instruction, MOV A,VNAME, things will go quite a bit faster even though the individual cycles are longer. Correct - it is always good to have a memory interface that can load the full instruction in one read. But your example requires 24 bits. Your previous post talked about 48 bits. Without a pipeline - what would you do with the information about the following instruction? Richard said:
I've not built an 805x core ... yet ... though I've done considerable preliminary work on it. I've built other cores, and have found that one can build nearly any MCU core with a simple two-phase clock, e.g. the sort which was used on 6801 or 6502, etc, [...] We are not talking about the use of a two-phase clock here. We are talking about managing the instruction with just two clock transitions. I was talking about one-clockers managing with just two phase changes without pipelining and without internal clock doublers. I know that the 6800 does not do 1MIPS at 1MHz. I haven't looked at the 6502, even if I know that it is using both phases of the clock and has asynchronous logic. Is it your claim the 6502 does 1 MIPS for 1MHz input clock? But was these two your proof of two-phase one-clockers? |
