When looking at a 48-bit-wide slice of code space, that "view" doesn't have to be pipelined. The primary objection to pipelining is the temporal impact on interrupt and RESET response. Having a wide view into the code space allows one to avoid temporal effects of pipelining, thereby making interrupt response delays minimal. It also means that arbitrarily long instructions (with the confines of the defined instruction set, of course) always execute in a single cycle. The rate at which that can be accomplished determines the overall performance of the core. That, in fact, is why some compromises have been made, over time, allowing some instructions to execute in multiple cycles. After all, if the resulting one-clocker will only execute instructions at 3 MIPS, you haven't gained much for your trouble.

RE