| ??? 05/16/09 23:26 Read: times |
#165432 - One step at a time Responding to: ???'s previous message |
Per Westermark said:
You continue to state this as a fact, all the time failing to notice the real world. Interrupt latency is not clock cycles until noticing an interrupt. The interrupt latency that matters is ns from interrupt source until the critical part of the interrupt has been serviced. No ... I believe the interrupt latency is the time from when the interrupt is recognized until the first byte of the interrupt service routine is being executed. However, with a pipeline, there's a large penalty afterward, in that, once the pipeline is flushed, the pipeline is loaded with the interrupt code, then entered, and completed, the pipeline has to be restored, else the prior process can't continue. Part of this problem, is because you think a pipeline is something that makes one instruction take more time. It makes one instruction consume more "machine cycles". No ... actually, it makes EVERYTHING in the machine take more machine cycles. But each machine cycle is simpler, allowing the same process geometry to run each machine cycle at a faster pace. So the total time of the instruction will not grow proportional to the number of steps in the pipeline. That's why they pipeline ... but it implicitly means more steps per instruction, and it's also why pipelining is seldom of use with "one-clockers" unless they also use a cache, which also introduces the same hassles as pipelining, among others. The second thing, is that the pipeline is concurrent. Most of the steps of the pipeline does something on every clock cycle. At the simplest (looking back 25-30 years), you just have staggered execution with overlapping: Yes, but it means more machine cycles per instruction, though it may require only one machine cycle per pipeline stage. However, since it makes each instruction consume more than one cycle, it's incompatible with pure one-clockers. Clock cycle: the time between corresponding edges of the external clock. Machine cycle: the time between rising corresponding edges of the system clock. Instruction cycle: The amount of time taken to execute, completely, the shortest of a processor's instructions. Ideally, in FPGA, one instruction cycle = one machine cycle = one propagation cycle, memory => ALU => memory, in the context of the architecture I mentioned before, wherein all ROM, RAM, SFR-space, and external memory are part of global memory. Clearly, that path is the rate-determining step. It requires no pipelining, and would benefit little from it. RE |
