Yes, architecture changes means that an implementation can take 5 clock cycles for one instruction and 1 for another, or in some situations run two instructions concurrently, making it look like the second instruction took zero clock cycles. So when moving between different cores, it isn't possible to just care about number of NOP/s at a given clock frequency. The real speed improvement will depend on the instruction mix and may scale significantly differently at a different instruction mix.

What make this interesting is that the original claim is "8.1 times faster than standard 80C51 at the same frequency", which means that we are not talking about a DT8051 at top speed being 8.1 times faster than a 12MHz 12-clocker. We are talking about a DT8051 clocked at 12MHz being 8.1 times faster. The 8.1 will increase when the DT8051 core is run at more than 12Mhz. And the factor 8.1 will decrease if you replace a 12MHz 12-clocker with a 33MHz 12-clocker.

In short, the claim is that the DT8051 has improved the (averaged) instruction efficiency for a specific benchmark with 8.1 times at the same clock frequency.

So, yes, I agree with you that the factor 8.1x in this case does not depend on CLK frequency but is a fixed efficiency factor, and only applicable when running a specific sequence of 8051 instructions. The fractional part of 8.1 gives a clear indication that it is not a computation simplified down to just NOP instructions, in which case we would have expected a figre 2, 3, 4, 6, 12, 24 (superscalar two-at-a-time processing)) or similar.

That is the reason why I wonder about the origin of the claim in Richards post, that it would take 300MHz for the DT8051 to match any 25MHz 1-clocker.