I think it's time you bought a book about Verilog. Palnitkar's is pretty good.

Anyways: dio is declared in the module definition as inout. dio are the chip's data I/O pins.

assign oe = (!RD_l && !CS_l);
assign dio = oe ? diomux : 8'bZZZZ_ZZZZ;

always @(*) begin : diomuxselect
    case ({A, ctrlword})
        CASE0 : diomux = ...;
        CASE1 : diomux = ...;
         ...
        CASEN : diomux = ...'
    endcase
end // diomuxselect

Note that the ONLY assignment TO dio is given above.

Again: when writing into the chip's various registers, the data source is always dio:

always @(posedge WR_l) begin : writeareg
    if (!CS_l && RD_L && (address compare here) ) begin
        reg <= dio;
    end
end // writeareg

And, again, when to read from the chip, make sure that the decoder diomuxselect above has a case for each register, where the register assigns to diomux. It's really not that complicated...

-a