Ports of mode buffer (see FAQ Part 4 - B.183 and FAQ Part 4 - B.157) can be both read and written. However, there is only a single source allowed to drive any net containing a buffer port, and that source must be internal to the port. While this restriction enables detection of unintended "multiple driver" errors during compilation (see also Section 4.2.13), a flaw in their definition makes them hard to use in the context of other designs. The following example is illegal in VHDL'87 and VHDL'93 because a port of mode out or inout must not be connected with a port of mode buffer:

entity SRLatch is
port( S, R: in bit;
Q, QBar: buffer bit); -- "Q" and "Qbar" are of
-- mode buffer!
end SRLatch;

architecture Structure of SRLatch is
component Nor2
port( I1, I2: in bit;
O: out bit); -- "O" is of mode out
end component;
begin
Q1: Nor2 port map (I1 => S, -- ok
I2 => QBar, -- ok
O => Q); -- illegal

Q2: Nor2 port map (I1 => R, -- ok
I2 => Q, -- ok
O => QBar); -- illegal
end Structure;

The component instantiation statements in this example are illegal because port "O" of "Nor2" is of mode "out" and hence cannot be associated with a buffer port. So, for the moment, the use of buffer ports may require that multiple libraries of standard cells be defined, one with out ports, the other with buffer ports. In most situations, this extra effort is not justified and therefore the use of buffer ports is discouraged.

However, the unnecessary restrictions on buffer ports were removed in VHDL 2000, so that buffer ports are more useful now (if your tool supports VHDL 2000).