| ??? 01/12/07 11:45 Read: times |
#130715 - regarding using seperate buses.. Responding to: ???'s previous message |
Jez Smith said:
ts always a bad idea to use bidirectional busses internaly to a design.Its much better to have two seperate busses and to merge them together at a higher level. I got the method you described jez. and willing to know regarding using seperate buses..
entity counter_load is
port ( bf_in : in std_logic_vector(7 downto 0); -- data bus in
bf_out: out std_logic_vector(7 downto 0); -- data bus out
ctr0_rw: in std_logic;
.
.
.
)end counter_load
As you are trying to load a 16 bit value into an 8 bit bus you need to split it over two phases.Something like
if rising edge(clk) then
if ctr0_RW='1' then
if done='0' then
if high_byte_flag='0' then
bf_out<=OLm;
high_byte_flag<='1'; --we know weve sent the high byte
else
bf_out<=OLl;
high_byte_flag<='0';
done<='1'; --transfer is finished
end if;
else
done<='0'; --reset transfer flag
end if;
end if;
if i use "bf_in" for writing, and "bf_out" for reading (as per your code (note: i have also named the output of my bidirectional databus buffer as "bf_out" in that module) then, can i connect "bf_in" to my bidirectional databus buffer(bf_out)by using the code shown below.. for write operations alone. module Internal_bus(bf_out,ctr0_select,ctr0_RW,bf_in); input [7:0]bf_out; //Bidirectional buffer output here declared as input input ctr0_select,ctr0_RW; output [7:0]bf_in;//lead to counter data input assign bf_in[7:0] = (ctr0_select == 1'b1 && ctr0_RW == 1'b1)?(bf_out[7:0]:8'bXXXXXXXX); regard's Suresh. |
