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???
01/12/07 21:01
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#130744 - Absolutely.
Responding to: ???'s previous message
Andy Peters said:

Does this make sense?
-a

Absolutely. You have given the general description of the entire 8254 architecture.

for your convenience.,

Here is the general block diagram.



and here is the block showing Counter block alone..



and here is the control word format that would be written to the ctrl word register.
Based on this data counter is getting selected , loaded and mode is programmed.



at present i have completed buffer,R/W logic and Control register blocks.
and now, implementing the counter block.
Here first iam concentrating on the Read and write operations alone.
Jez said:

The fact that the port of the 'out' signal is in out mode is what you want for it to be readable by the status register.

iam doing the whole counter block in a single module.
In that case, how could i assign the 'out' value (being mode 'output')to the status register bit.
could you be little descriptive.

regard's
Suresh.







List of 28 messages in thread
TopicAuthorDate
data flow modeling in Verilog            01/01/70 00:00      
   How to post code            01/01/70 00:00      
   proper code...            01/01/70 00:00      
      Break up your code into smaller pieces            01/01/70 00:00      
         Thanks            01/01/70 00:00      
         what does that have to do with verilog? :)            01/01/70 00:00      
      Verilog bites like C            01/01/70 00:00      
         yes sorry. i made a mistake there.            01/01/70 00:00      
      ugh            01/01/70 00:00      
         details            01/01/70 00:00      
            dont use a bidirectional bus            01/01/70 00:00      
               regarding using seperate buses..            01/01/70 00:00      
                  out signal to status register            01/01/70 00:00      
                     hints            01/01/70 00:00      
                        Absolutely.            01/01/70 00:00      
                        Since \'diomux\' is a register....            01/01/70 00:00      
                           re: Since 'diomux' is a register ...            01/01/70 00:00      
                              regarding write and read operations...            01/01/70 00:00      
                                 re: regarding write and read ops            01/01/70 00:00      
                                    thank you..            01/01/70 00:00      
   Yukky verilog            01/01/70 00:00      
      Yes i did            01/01/70 00:00      
   all you do is...            01/01/70 00:00      
       can i do like this.,            01/01/70 00:00      
         if it's in BUFFER mode ...            01/01/70 00:00      
            buffer mode ports from the vhdl faq            01/01/70 00:00      
         mode out on RHS            01/01/70 00:00      
            very good Solutions!            01/01/70 00:00      

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