| ??? 01/11/07 19:07 Read: times |
#130691 - ugh Responding to: ???'s previous message |
Suresh R said:
assign bf_out = (ctr0_slect = 1'b1 && ctr0_RW = 1'b0)?(rd_bk = 1'b1 && ctrl_data[4] = 1'b0? status_latch:[5:4]ctrl_data = 2'b01?OLl:[5:4]ctrl_data = 2'b10?OLm:[5:4]ctrl_data = 2'b11??... Ugh, where to begin? The bit-selects [5:4] belong AFTER the reg/wire name, i.e., foo = bar[5:4](assuming foo is two bits wide). In the above code sample, LHS 'net' bf_out is 8- bit and all the 'reg' on RHS are also 8 - bit each.
Here for the combination "[5:4]ctrl_data = 2'b11" i need to send both OLl and OLm (OLl 8 bit and OLm 8 bit)to bf_out. can any one tell me whether it could be done using assign statement. You can't "send" (which I read as "assign") two 8-bit signals to one 8-bit signal at the same time; that makes no sense. You're basically building a mux with a somewhat-complicated selector. Break up your code into two assignment statements, one to deal with the selector and one to do the mux assign based on that selector. You could also do the whole thing in an always block. Just don't string everything along in one huge messy line. If I was reviewing your code, I'd bounce it back. -a |
