first, you must realize that most modern FPGA families don't have internal tri-state buses (which was a feature on the XC4000 parts that I used to good advantage). Some synthesis tools may translate internal tri-states to muxes, but I don't recommend doing that ... write the code to use muxes.

Now, even though the block diagram has an "internal bus," you can work around that in the following way: every item on the block diagram that gets its input FROM the "internal bus" (like the control word, CRm and CRl registers) needs to have a mux on its input that selects from the possible sources (which means you really need to understand the chip architecture). If it turns out that these registers are loaded ONLY from the chip's data I/O pins D[7:0], then you don't need a mux; all you need to do is decode the control stuff to load the registers at the right time.

Driving the various outputs on the data I/O pins will require a mux and a tristate. The control logic for the mux should be kept separate from the tristate logic. The output drivers are turned on only when RD\ and CS\ are asserted; otherwise they remain 8'bZZZZZZZZ. The mux select logic can ignore RD\ and CS\ entirely. Use state of A[1:0] and the value of any previously-loaded control word as your mux select.

It'll be something like this:

assign oe = (!RD_l && !CS_l);
assign dio = oe ? diomux : 8'bZZZZ_ZZZZ;

always @(*) begin : diomuxselect
    case ({A, ctrlword})
        CASE0 : diomux = ...;
        CASE1 : diomux = ...;
         ...
        CASEN : diomux = ...'
    endcase
end // diomuxselect

Note that diomux must be declared as an 8-bit reg.

Writing is similar. Writes are enabled when WR\ and CS\ are asserted. (Perhaps WR\ can be a global clock, with CS\ as its enable?) You write a command to the control word register by driving A[1:0] == 2'b11. You then write data words corresponding to that control word (initial count value, whatever) by addressing a counter (using A[1:0]).

Does this make sense?

-a