Email: Password: Remember Me | Create Account (Free)

Back to Subject List

Old thread has been locked -- no new posts accepted in this thread
???
01/11/07 18:37
Read: times


 
#130685 - what does that have to do with verilog? :)
Responding to: ???'s previous message
Break up your code into smaller pieces

Is universal


Erik

List of 28 messages in thread
TopicAuthorDate
data flow modeling in Verilog            01/01/70 00:00      
   How to post code            01/01/70 00:00      
   proper code...            01/01/70 00:00      
      Break up your code into smaller pieces            01/01/70 00:00      
         Thanks            01/01/70 00:00      
         what does that have to do with verilog? :)            01/01/70 00:00      
      Verilog bites like C            01/01/70 00:00      
         yes sorry. i made a mistake there.            01/01/70 00:00      
      ugh            01/01/70 00:00      
         details            01/01/70 00:00      
            dont use a bidirectional bus            01/01/70 00:00      
               regarding using seperate buses..            01/01/70 00:00      
                  out signal to status register            01/01/70 00:00      
                     hints            01/01/70 00:00      
                        Absolutely.            01/01/70 00:00      
                        Since \'diomux\' is a register....            01/01/70 00:00      
                           re: Since 'diomux' is a register ...            01/01/70 00:00      
                              regarding write and read operations...            01/01/70 00:00      
                                 re: regarding write and read ops            01/01/70 00:00      
                                    thank you..            01/01/70 00:00      
   Yukky verilog            01/01/70 00:00      
      Yes i did            01/01/70 00:00      
   all you do is...            01/01/70 00:00      
       can i do like this.,            01/01/70 00:00      
         if it's in BUFFER mode ...            01/01/70 00:00      
            buffer mode ports from the vhdl faq            01/01/70 00:00      
         mode out on RHS            01/01/70 00:00      
            very good Solutions!            01/01/70 00:00      

Back to Subject List