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???
01/11/07 18:35
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 		 #130683 - Verilog bites like C
Responding to: ???'s previous message
Suresh R said:
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assign bf_out = (ctr0_slect = 1'b1 && ctr0_RW = 1'b0)?(rd_bk = 1'b1 && ctrl_data[4] = 1'b0?
status_latch:[5:4]ctrl_data = 2'b01?OLl:[5:4]ctrl_data = 2'b10?OLm:[5:4]ctrl_data = 2'b11??...

The equality operator in Verilog is the same as it is in C, which is to say
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assign foo = (foosel == FOOBAR)? bar : bletch;
Note two equal signs, not one, between foosel and FOOBAR. And, like C, it'll bite you in the ass if you mistake one for the other (although some tools may throw out a helpful warning).

Then there's the case equality, which is THREE equal signs...

-a

List of 28 messages in thread
TopicAuthorDate
data flow modeling in Verilog            01/01/70 00:00      
   How to post code            01/01/70 00:00      
   proper code...            01/01/70 00:00      
      Break up your code into smaller pieces            01/01/70 00:00      
         Thanks            01/01/70 00:00      
         what does that have to do with verilog? :)            01/01/70 00:00      
      Verilog bites like C            01/01/70 00:00      
         yes sorry. i made a mistake there.            01/01/70 00:00      
      ugh            01/01/70 00:00      
         details            01/01/70 00:00      
            dont use a bidirectional bus            01/01/70 00:00      
               regarding using seperate buses..            01/01/70 00:00      
                  out signal to status register            01/01/70 00:00      
                     hints            01/01/70 00:00      
                        Absolutely.            01/01/70 00:00      
                        Since \'diomux\' is a register....            01/01/70 00:00      
                           re: Since 'diomux' is a register ...            01/01/70 00:00      
                              regarding write and read operations...            01/01/70 00:00      
                                 re: regarding write and read ops            01/01/70 00:00      
                                    thank you..            01/01/70 00:00      
   Yukky verilog            01/01/70 00:00      
      Yes i did            01/01/70 00:00      
   all you do is...            01/01/70 00:00      
       can i do like this.,            01/01/70 00:00      
         if it's in BUFFER mode ...            01/01/70 00:00      
            buffer mode ports from the vhdl faq            01/01/70 00:00      
         mode out on RHS            01/01/70 00:00      
            very good Solutions!            01/01/70 00:00      

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