Hi,
i would like to know how i could transfer a 16 bit data to a 8 bit bus using "assign" statement in Verilog.

here is the code sample.,
assign bf_out = (ctr0_slect = 1'b1 && ctr0_RW = 1'b0)?(rd_bk = 1'b1 && ctrl_data[4] = 1'b0)?
status_latch:[5:4]ctrl_data = 2'b01?(OLl):([5:4]ctrl_data = 2'b10)?(OLm):([5:4]ctrl_data = 2'b11??...

In the above code sample LHS 'net' bf_out is 8- bit and all the 'reg' on RHS are also 8 - bit.
Here for the combination "[5:4]ctrl_data = 2'b11" i need to send both OLl and OLm (OLl 8 bit and OLm 8 bit)to bf_out.
can any one tell me whether it could be done using assign statement.

regard's
Suresh.