Signals declared as entity out types in VHDL cannot be used on the RHS of an assignment. (This restriction was relaxed in the latest versions of VHDL, but I don't know which tools support this.)

So the usual solution is to use a dummy signal that's the source and target for any assignments that need the signal driven OUT. The only use of the actual OUT signal is an assignment to it from the dummy. For example:

entity foo is
    port (
    clk : in std_logic;
    d   : in std_logic;
    q   : out std_logic;
    q_l : out std_logic);
end entity foo;

architecture bar of foo is
    signal q_i : std_logic;  -- "dummy" internal q
begin
    q   <= q_i;      -- use dummy because 
    q_l <= not q_i;  -- we can't do q_l <= not q

    flop : process (clk) is
    begin
        q_i <= d;
    end process flop;
end architecture bar;

And don't use BUFFER ... it's a minefield best avoided.

-a