It is hard to understand Verilog when everything is in a single statement. Try breaking it up into smaller statements. Calculate the variable that controls the bus, and then use it.

For example:

wire [7:0] bf_out, OLm, OLl;
wire read_high;

assign read_high = .... ;
assign bf_out = read_high ? OLm : OLl ;

Let read_high be the condition for the upper byte, and the lower byte goes out by default.

As with any big problem, it's usually a good idea to break it into smaller problems that are easier to solve.