All you do if you want to latch a signal is define what happens in one state but not in the other,so for example in vhdl again you could say something like

if rising_edge(clk) then
if status_read='1' then
status<=status_bit1 & status_bit2 & ect and so on;
end if;
end if;

which infers a latch because if status_read isnt ='1' then nothing happens and the value written to status remains the same.Its actualy a classic beginners mistake to infer a latch thet wasnt intended by not fully specifying a conditional clause,in this case it is intended.The fact that the port of the 'out' signal is in out mode is what you want for it to be readable by the status register.