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???
01/13/07 05:27
Modified:
  01/13/07 05:36

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#130764 - Since \'diomux\' is a register....
Responding to: ???'s previous message
Andy Peters said:

If it turns out that these registers are loaded ONLY from the chip's data I/O pins D[7:0], then you don't need a mux; all you need to do is decode the control stuff to load the registers at the right time.

Yes. Thats is what i need to do.

Driving the various outputs on the data I/O pins will require a mux and a tristate. The control logic for the mux should be kept separate from the tristate logic.It'll be something like this:
assign oe = (!RD_l && !CS_l);
assign dio = oe ? diomux : 8'bZZZZ_ZZZZ;

always @(*) begin : diomuxselect
    case ({A, ctrlword})
        CASE0 : diomux = ...;
        CASE1 : diomux = ...;
         ...
        CASEN : diomux = ...'
    endcase
end // diomuxselect

Note that diomux must be declared as an 8-bit reg.
Writing is similar.
-a

Since 'diomux' is a register how could i use it on the LHS of 'assign' statement during write operations?

regard's
Suresh.





List of 28 messages in thread
TopicAuthorDate
data flow modeling in Verilog            01/01/70 00:00      
   How to post code            01/01/70 00:00      
   proper code...            01/01/70 00:00      
      Break up your code into smaller pieces            01/01/70 00:00      
         Thanks            01/01/70 00:00      
         what does that have to do with verilog? :)            01/01/70 00:00      
      Verilog bites like C            01/01/70 00:00      
         yes sorry. i made a mistake there.            01/01/70 00:00      
      ugh            01/01/70 00:00      
         details            01/01/70 00:00      
            dont use a bidirectional bus            01/01/70 00:00      
               regarding using seperate buses..            01/01/70 00:00      
                  out signal to status register            01/01/70 00:00      
                     hints            01/01/70 00:00      
                        Absolutely.            01/01/70 00:00      
                        Since \'diomux\' is a register....            01/01/70 00:00      
                           re: Since 'diomux' is a register ...            01/01/70 00:00      
                              regarding write and read operations...            01/01/70 00:00      
                                 re: regarding write and read ops            01/01/70 00:00      
                                    thank you..            01/01/70 00:00      
   Yukky verilog            01/01/70 00:00      
      Yes i did            01/01/70 00:00      
   all you do is...            01/01/70 00:00      
       can i do like this.,            01/01/70 00:00      
         if it's in BUFFER mode ...            01/01/70 00:00      
            buffer mode ports from the vhdl faq            01/01/70 00:00      
         mode out on RHS            01/01/70 00:00      
            very good Solutions!            01/01/70 00:00      

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