Thanks for giving those corrections Andy.
Actually i am going on with implementing 8254 Interval Timer using Verilog.
The code sample i posted here is to perform data transfer between the 8 bit Internal bus(bf_out) and a counter block.
Since the internal bus(bf_out) is bidirectional(inout) i couldnt use it within "always" statement.
The figure below shows the internal block diagram of the counter.



So the problem i have is,

When "ctrl_data[5:4] == 2'b11" //control reg value that says R/W MSB first then LSB.

-For Read Operations (i.e.,if ctr0_RW == 1'b0),

i need to read OLm(8 bit) first then OLl(8 bit) through the bus (bf_out)
I have done this as below.

assign bf_out[7:0] = (ctr0_select == 1'b1 && ctr0_RW == 1'b0)?(temp_bus[7:0]:8'bXXXXXXXX);

Comment: temp_bus is a temporary register i use to which OLm and OLl values are sent using an always statement when a "ctrl_data[5:4] == 2'b11" and a read signal(ctr0_RW = 1'b0) is encounterd.

But for write operations,
i.e.,when "ctrl_data[5:4] == 2'b11" and ctr0_RW == 1'b1.,
i need to load MSB in CRm(8 bit) and LSB in CRl(8 bit)
i couldnt find a better idea to perform it since internal bus(bf_out) is a "net".

Can i get some suggestions in it.
I also welcome any better ideas.

regard's
Suresh.