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??? 04/29/07 19:47 Read: times	#138231 - Thanks Richard Responding to: ???'s previous message

List of 54 messages in thread

Topic	Author	Date
VHDL FPGA		01/01/70 00:00
Hello, world?		01/01/70 00:00
LCD display		01/01/70 00:00
video overlay		01/01/70 00:00
funny you should say that		01/01/70 00:00
bcd to binary		01/01/70 00:00
Try a different algorithm		01/01/70 00:00
easier way		01/01/70 00:00
LUT		01/01/70 00:00
This is what you want!		01/01/70 00:00
It is not as easy as it seems!		01/01/70 00:00
Here\'s a little exercise ...		01/01/70 00:00
more info required		01/01/70 00:00
I don't think its very fair.		01/01/70 00:00
consider this ...		01/01/70 00:00
pick an arbitrary frequency		01/01/70 00:00
warnings		01/01/70 00:00
Give us a clue,what do they say?		01/01/70 00:00
warnings sample		01/01/70 00:00
You can ignore most of them, but Quartus is buggy		01/01/70 00:00
Combinational Loops		01/01/70 00:00
No doubt about it ...		01/01/70 00:00
gated/ripple clocks		01/01/70 00:00
... but those complaints aren\'t always relevant		01/01/70 00:00
warnings		01/01/70 00:00
Andy, how would YOU construct a latch?		01/01/70 00:00
latches in FPGAs		01/01/70 00:00
Excellent Posting		01/01/70 00:00
more about latches		01/01/70 00:00
I like clear terms in my latches		01/01/70 00:00
The point is i think ... unitentional latches		01/01/70 00:00
exactly ...		01/01/70 00:00
elsif		01/01/70 00:00
Bad code		01/01/70 00:00
elsif		01/01/70 00:00
Quartus complains if you use the library latch		01/01/70 00:00
latch reset inputs		01/01/70 00:00
the library latch has no clear function		01/01/70 00:00
Brand A vs Brand X		01/01/70 00:00
true enough		01/01/70 00:00
Modelsim		01/01/70 00:00
about the only limitations on modelsim are ;-		01/01/70 00:00
ModelSim, PicoBlaze, MicroBlaze		01/01/70 00:00
there's a CPLD <=>LCD app note		01/01/70 00:00
JTAG interface		01/01/70 00:00
darn		01/01/70 00:00
Xilinx CPLD applications handbook		01/01/70 00:00
Mahmood, stick with the recommended circuit		01/01/70 00:00
Recommended circuit		01/01/70 00:00
I would be really careful ...		01/01/70 00:00
Thanks Richard		01/01/70 00:00
don't be distracted by the unnecessary parts		01/01/70 00:00
Xilinx Jtag for Altera		01/01/70 00:00
How about Altera JTAG for ALTERA		01/01/70 00:00

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