Mahmood,

With digital PLL's the frequency isn't terribly important, but the ratio of the driver clock (16x in this case) to the reference signal, is what's critical, as that defines the input and output granularity. In this case, however, from the time that you start to sample a signal until you run out of sync field, you have be fairly quick in order to have the densest input.

If you want, you can use a 10 MHz reference and a 160 MHz (16x)driver clock. It doesn't really matter whether it's 1 Hz or 10 GHz, o ranywhere between the two, though.

When the local driver clock (a fixed-frequency oscillator) differs from the timebase used in generating the reference by 100 ppm or less, at some point there will come a time when the two timebases force the phase detection relationships to reverse. It's during that interval that the "intersting" things happen. That's what will have you scratching your head. The simulator, irrespective of which one it is, will have difficulty showing you what happens during this mysterious interval, because it can't cope with udnefined events well enough to recover. It's possible to detect undefined/metastabile events in the logic with some additional logic, and that can make it possible for you to work around the problems. I'll leave that for you to "enjoy," however.

I wouldn't expend any effort on using the DLL, except, perhaps, to multiply or phase-shift the input clock. This is because the DLL doesn't like missing pulses and it interprets 180-degree phase shifts as excessive jitter that causes it to lose lock.

Think about what an analog PLL does. It has a phase-detector, the purpose of which is to detect and quantify the phase difference between the reference input and the driver oscillator. It has an error amplifier by means of which it determines the magnitude of the correction to the output that each phase difference detection will create, and it has a voltage-controlled oscillator which responds to that error voltage output. In an all-digital PLL, we have a fixed local oscillator, rather than one the frequency of which we can alter. We can, however, incrementally change the phase difference. The error amplifier determines the magnitude (gain) of the phase error, and the ratio of the local (driver) oscillator to the nominal frequency of the local (driver) oscillator provides that function.

If you think about how you can adjust the phase of the output clock to match the phase of the input clock, without worrying about loop filter equations, or phase detector gain, vco gain, etc, you'll be fine. Don't think about applying signal processing techniques, as is done in cellphones, to the DPLL, becuase that will make it orders of magnitude slower.

RE