I think the real reason the FPGA tools WARN you about latches is because in many (most?) cases in a synchronous design, they're the result of typos. Perhaps the engineer missed a signal in a sensitivity list, or missed adding an "else" clause to an "if" statement in a combinatorial process. What typically happens is that the synthesis result won't match the simulation (a Bad Thing).

Maybe synthesis tools should allow for a "latch" attribute on a signal, which tells the tools "Yes, I know that this signal is a latch, so shaddup already!"

signal q : std_logic_vector(7 downto 0);
attribute latch : string;
attribute latch of q : signal is "yes";

mylatch : process (le, d) is
begin
    latchenable : if (le = '1') then
        q <= d;
    end if latchenable;
end process mylatch;

-a