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???
04/20/07 18:41
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#137666 - ModelSim, PicoBlaze, MicroBlaze
Responding to: ???'s previous message
Mahmood Elnasser said:
1. I just downloaded the evaluation version of modelsim to practice some test benches on it. Is this version as good as the full version? do you know of any limitations?


There are some "professional" features missing (various code coverage tools, and things you've never heard about). The "free" ModelSim XE is slower than paid-for PE and SEE, and will slow down further if the number of lines of code exceeds some magic number. (I've exceeded that magic number doing a backannotated timing sim with VITAL models. It was unusable. The good news is that you rarely need to run a timing sim.)

2. I was reading about picoblaze microcontroller core from xilinx. It is very bad microcontroller compared to real 8052, dspic etc in terms of programming instructions.


If you'd further read about it, you'd realize that it was never intended to replace an 8051 or a PIC. Its design criteria were: small (use very few resources) and simple instruction set with constant timing. To that end, it succeeds -- I have PicoBlazes running in two designs right now. It's called a "processor" but it's really a programmable state machine. I use the PicoBlazes for things where a traditional state machine just gets real ugly.

My question is isn't it better to use external microcontroller and program it with decent instruction sets or C language and interface it to normal FPGA or CPLD to get the best of both worlds. I know if you do it inside the fpga you save on pcb space and achieve higher operating speed due to short busses inside the fpga but is the hassle of programming the core with lousy instruction set worth it?


As in all things: it depends. If you need the extra features of many microcontrollers, then you use the micro. In some cases, a microcontroller may be overkill. In other cases, an external microcontroller isn't embedded deep enough with the rest of the FPGA fabric and you need clock-to-clock turnaround.

In other cases, the microcontroller is the only way to go, especially if you need the timer resources, the interrupts, some comparators, DACs, ADCs and other features.

Pick the right tool for the job. Don't just shove an 8051 in there because you're comfortable with it.

3. I'm going to build my first CPLD board next monday to control HD44780 LCD. Hope the XC9572XL I have will have enuf resources to do the job otherwise I have to think about another project.


Ah, but think about how you'll get data TO the CPLD so it has something interesting to display ...

-a




List of 54 messages in thread
TopicAuthorDate
VHDL FPGA            01/01/70 00:00      
   Hello, world?            01/01/70 00:00      
      LCD display            01/01/70 00:00      
         video overlay            01/01/70 00:00      
            funny you should say that            01/01/70 00:00      
   bcd to binary            01/01/70 00:00      
      Try a different algorithm            01/01/70 00:00      
      easier way            01/01/70 00:00      
         LUT            01/01/70 00:00      
   This is what you want!            01/01/70 00:00      
      It is not as easy as it seems!            01/01/70 00:00      
   Here\'s a little exercise ...            01/01/70 00:00      
      more info required            01/01/70 00:00      
         I don't think its very fair.            01/01/70 00:00      
            consider this ...            01/01/70 00:00      
         pick an arbitrary frequency            01/01/70 00:00      
   warnings            01/01/70 00:00      
      Give us a clue,what do they say?            01/01/70 00:00      
         warnings sample            01/01/70 00:00      
            You can ignore most of them, but Quartus is buggy            01/01/70 00:00      
               Combinational Loops            01/01/70 00:00      
                  No doubt about it ...            01/01/70 00:00      
            gated/ripple clocks            01/01/70 00:00      
               ... but those complaints aren\'t always relevant            01/01/70 00:00      
            warnings            01/01/70 00:00      
               Andy, how would YOU construct a latch?            01/01/70 00:00      
                  latches in FPGAs            01/01/70 00:00      
                     Excellent Posting            01/01/70 00:00      
                     more about latches            01/01/70 00:00      
                        I like clear terms in my latches            01/01/70 00:00      
                           The point is i think ... unitentional latches            01/01/70 00:00      
                              exactly ...            01/01/70 00:00      
                                 elsif            01/01/70 00:00      
                                    Bad code            01/01/70 00:00      
                                    elsif            01/01/70 00:00      
                                 Quartus complains if you use the library latch            01/01/70 00:00      
                           latch reset inputs            01/01/70 00:00      
                              the library latch has no clear function            01/01/70 00:00      
                                 Brand A vs Brand X            01/01/70 00:00      
                                    true enough            01/01/70 00:00      
   Modelsim            01/01/70 00:00      
      about the only limitations on modelsim are ;-            01/01/70 00:00      
      ModelSim, PicoBlaze, MicroBlaze            01/01/70 00:00      
         there's a CPLD <=>LCD app note            01/01/70 00:00      
            JTAG interface            01/01/70 00:00      
            darn            01/01/70 00:00      
               Xilinx CPLD applications handbook            01/01/70 00:00      
   Mahmood, stick with the recommended circuit            01/01/70 00:00      
      Recommended circuit            01/01/70 00:00      
         I would be really careful ...            01/01/70 00:00      
            Thanks Richard            01/01/70 00:00      
               don't be distracted by the unnecessary parts            01/01/70 00:00      
                  Xilinx Jtag for Altera            01/01/70 00:00      
                     How about Altera JTAG for ALTERA            01/01/70 00:00      

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