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???
04/15/07 22:40
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#137303 - warnings sample
Responding to: ???'s previous message
The first warning is legitmate because I'm still working on the tri_address for i need to think how to do a triangle waveform. but the rest I have no clue.
Warning (10541): VHDL Signal Declaration warning at funcgen.vhd(40): used implicit default value for signal "tri_address" because signal
 was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10631): VHDL Process Statement warning at kb_encoder.vhd(172): inferring latch(es) for signal or variable "kbrtn_encod", which 
holds its previous value in one or more paths through the process
Warning: Removed always-enabled tri-state buffer ROM:ROM1|lpm_rom:lpm_rom_component|otri[0] feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer ROM:ROM1|lpm_rom:lpm_rom_component|otri[1] feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer ROM:ROM1|lpm_rom:lpm_rom_component|otri[2] feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer ROM:ROM1|lpm_rom:lpm_rom_component|otri[3] feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer ROM:ROM1|lpm_rom:lpm_rom_component|otri[4] feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer ROM:ROM1|lpm_rom:lpm_rom_component|otri[5] feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer ROM:ROM1|lpm_rom:lpm_rom_component|otri[6] feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer ROM:ROM1|lpm_rom:lpm_rom_component|otri[7] feeding logic, open-drain buffer, or output pin
Warning: Latch kb_encoder:KEY_BOARD|kbrtn_encod[0] has unsafe behavior
	Warning: Ports D and ENA on the latch are fed by the same signal kb_rtrn[2]
Warning: Latch kb_encoder:KEY_BOARD|kbrtn_encod[1] has unsafe behavior
	Warning: Ports D and ENA on the latch are fed by the same signal kb_rtrn[1]
Warning: Timing Analysis is analyzing one or more combinational loops as latches
	Warning: Node "kb_encoder:KEY_BOARD|kbrtn_encod[0]" is a latch
	Warning: Node "kb_encoder:KEY_BOARD|kbrtn_encod[1]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
	Info: Assuming node "f_clk" is an undefined clock
	Info: Assuming node "kb_rtrn[3]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
	Info: Assuming node "kb_rtrn[2]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
	Info: Assuming node "kb_rtrn[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
	Info: Assuming node "kb_rtrn[0]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as
 buffer(s) resulting in clock skew


List of 54 messages in thread
TopicAuthorDate
VHDL FPGA            01/01/70 00:00      
   Hello, world?            01/01/70 00:00      
      LCD display            01/01/70 00:00      
         video overlay            01/01/70 00:00      
            funny you should say that            01/01/70 00:00      
   bcd to binary            01/01/70 00:00      
      Try a different algorithm            01/01/70 00:00      
      easier way            01/01/70 00:00      
         LUT            01/01/70 00:00      
   This is what you want!            01/01/70 00:00      
      It is not as easy as it seems!            01/01/70 00:00      
   Here\'s a little exercise ...            01/01/70 00:00      
      more info required            01/01/70 00:00      
         I don't think its very fair.            01/01/70 00:00      
            consider this ...            01/01/70 00:00      
         pick an arbitrary frequency            01/01/70 00:00      
   warnings            01/01/70 00:00      
      Give us a clue,what do they say?            01/01/70 00:00      
         warnings sample            01/01/70 00:00      
            You can ignore most of them, but Quartus is buggy            01/01/70 00:00      
               Combinational Loops            01/01/70 00:00      
                  No doubt about it ...            01/01/70 00:00      
            gated/ripple clocks            01/01/70 00:00      
               ... but those complaints aren\'t always relevant            01/01/70 00:00      
            warnings            01/01/70 00:00      
               Andy, how would YOU construct a latch?            01/01/70 00:00      
                  latches in FPGAs            01/01/70 00:00      
                     Excellent Posting            01/01/70 00:00      
                     more about latches            01/01/70 00:00      
                        I like clear terms in my latches            01/01/70 00:00      
                           The point is i think ... unitentional latches            01/01/70 00:00      
                              exactly ...            01/01/70 00:00      
                                 elsif            01/01/70 00:00      
                                    Bad code            01/01/70 00:00      
                                    elsif            01/01/70 00:00      
                                 Quartus complains if you use the library latch            01/01/70 00:00      
                           latch reset inputs            01/01/70 00:00      
                              the library latch has no clear function            01/01/70 00:00      
                                 Brand A vs Brand X            01/01/70 00:00      
                                    true enough            01/01/70 00:00      
   Modelsim            01/01/70 00:00      
      about the only limitations on modelsim are ;-            01/01/70 00:00      
      ModelSim, PicoBlaze, MicroBlaze            01/01/70 00:00      
         there's a CPLD <=>LCD app note            01/01/70 00:00      
            JTAG interface            01/01/70 00:00      
            darn            01/01/70 00:00      
               Xilinx CPLD applications handbook            01/01/70 00:00      
   Mahmood, stick with the recommended circuit            01/01/70 00:00      
      Recommended circuit            01/01/70 00:00      
         I would be really careful ...            01/01/70 00:00      
            Thanks Richard            01/01/70 00:00      
               don't be distracted by the unnecessary parts            01/01/70 00:00      
                  Xilinx Jtag for Altera            01/01/70 00:00      
                     How about Altera JTAG for ALTERA            01/01/70 00:00      

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