You have four input signals, which enter the fpga through a 4:1 multiplexer, the timebase for each of which is different but within 100 ppm nominal. Each signal is in bursts of 1536 byte length, including a 7-byte sync field of alternating ones and zeroes, (sound familiar?) at the beginning of a data packet and ending in a pattern of 1011, called a start of frame delimiter. The data is manchester encoded. Modulated random (not really, but more or less) immediately follows the SFD and ends in CRC32.

Your task is to utilize the system global clock of 16x the data rate to acquire and lock to the selected data such that you can produce 4 quadrature clocks in synchronization with the incoming data and tracking it, making small (1/16) phase adjustments despite the occasional frame-slip due to the .01% or less differences in frequency. You must never allow more than 1/16 clock period of error in synchronization between the input signal and the four quadrature clocks.

That should keep you busy and out of trouble for a while.

Good Luck!

RE

P.S. I've got several solutions, none of which make me particularly happy, but any of which seem to work equally well, and none of which are in VHDL/Verilog.