Yes, there are hazards in combinatorial loops, but if you want a latch you've got to use one, don't you? You can, of course, use one that uses two logic elements, but since it's possible to generate the same function with one, well, you get the idea. In the case of ALTERA's Quartus software, whether you create the latch in FPGA or CPLD, it amounts to the same warning, even when using a library member latch, e.g, 74373. It also "warns" of the non-use of a tristate buffer that's part of the library component.

I don't like the Quartus software's habit of changing signal names associated with busses in so arbitrarily. If I have A(15..0) and D(7..0) it almost always changes A(nn) to Ann, yet leaves D(k) alone. I don't understand that. I don't like it, either. What's more, I complained about that back in '02, yet they haven't yet fixed it, and it was already reported, though not by me, in '97 or so in MaxPlus+ II, where it originated.

Those Altera guys just don't display much diligence with the repair of software bugs.

For stuff that's going to be manufactured and assembled here, I don't use Altera FPGA's, either, as they only have TQFP 100 and 144's. BGA's lead to a requirement for Asian manufacturing and assembly, since they'll take the employee who screws up and shoot him, subsequently selling his recyclable parts to compensate them for the loss due to his screwup. If they did that here, we'd have 0.3 mil registration between drilled and etched features, and between layers, and the BGA's wouldn't be soldered on only 99% of their balls.

RE