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???
04/29/07 18:39
Modified:
  04/29/07 18:57

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#138227 - I would be really careful ...
Responding to: ???'s previous message
I can't find an FPGA on the DIO2, but the programming circuit is probably sound. I'd be careful, however, and ensure that the programming circuit meets the spec's set forth by XILINX themselves.

There's an app-note somewhere ... Hmmm ... here it is ...

I've had no trouble with the JTAG interfaces that Digilent has built into their boards. I've had no trouble with the ones that others have built for use with JTAG. On a lark, I bought one from a Canadian company, that cost ~$26CN including shipping, IIRC, and works just fine, too, though its "flying leads" are a mite flimsy.

If you carefully reproduce the circuit on the Digilent board, having understood the basics of how JTAG connections must be implemented, I think you'll have no trouble reproducing their work.

I'd recommend you take a careful look at some of the later DIGILENT boards, particularly ones that use the circuit that you intend to program. I personally have a number of Digilent boards and the programming cables that came with them, and they all seem to work just fine. All they have done in the later boards is conform to a widely used standard pinout, promoted by XILINX. If you look at

http://www.xilinx.com/support/s...d/jtag.pdf

I think you can figure out how to build an equivalent cable with minimal risk of vailure, and of damaging anything.

As you've probably seen many times, DON'T DEVIATE FROM THE RECOMMENDED SCHEMATIC! If you fail to heed this advice, you're on your own.

BTW, there's a slight drafting error on the schematic, namely that both U1 and U2 are 'HC125's, which should tell you that you probably CAN use both halves of a 74HC244 independently as the DIGILENT people have done ... and the term serial, just to avoid confusion, refers to serial numbers.

Now, the Digilent folks did things a bit differently, but if you study both circuits, you'll see what's necessary. I'd point out that the function is what matters, and that the DIGILENT hardware works fine with the XILINX programming software (IMPACT).

RE



List of 54 messages in thread
TopicAuthorDate
VHDL FPGA            01/01/70 00:00      
   Hello, world?            01/01/70 00:00      
      LCD display            01/01/70 00:00      
         video overlay            01/01/70 00:00      
            funny you should say that            01/01/70 00:00      
   bcd to binary            01/01/70 00:00      
      Try a different algorithm            01/01/70 00:00      
      easier way            01/01/70 00:00      
         LUT            01/01/70 00:00      
   This is what you want!            01/01/70 00:00      
      It is not as easy as it seems!            01/01/70 00:00      
   Here\'s a little exercise ...            01/01/70 00:00      
      more info required            01/01/70 00:00      
         I don't think its very fair.            01/01/70 00:00      
            consider this ...            01/01/70 00:00      
         pick an arbitrary frequency            01/01/70 00:00      
   warnings            01/01/70 00:00      
      Give us a clue,what do they say?            01/01/70 00:00      
         warnings sample            01/01/70 00:00      
            You can ignore most of them, but Quartus is buggy            01/01/70 00:00      
               Combinational Loops            01/01/70 00:00      
                  No doubt about it ...            01/01/70 00:00      
            gated/ripple clocks            01/01/70 00:00      
               ... but those complaints aren\'t always relevant            01/01/70 00:00      
            warnings            01/01/70 00:00      
               Andy, how would YOU construct a latch?            01/01/70 00:00      
                  latches in FPGAs            01/01/70 00:00      
                     Excellent Posting            01/01/70 00:00      
                     more about latches            01/01/70 00:00      
                        I like clear terms in my latches            01/01/70 00:00      
                           The point is i think ... unitentional latches            01/01/70 00:00      
                              exactly ...            01/01/70 00:00      
                                 elsif            01/01/70 00:00      
                                    Bad code            01/01/70 00:00      
                                    elsif            01/01/70 00:00      
                                 Quartus complains if you use the library latch            01/01/70 00:00      
                           latch reset inputs            01/01/70 00:00      
                              the library latch has no clear function            01/01/70 00:00      
                                 Brand A vs Brand X            01/01/70 00:00      
                                    true enough            01/01/70 00:00      
   Modelsim            01/01/70 00:00      
      about the only limitations on modelsim are ;-            01/01/70 00:00      
      ModelSim, PicoBlaze, MicroBlaze            01/01/70 00:00      
         there's a CPLD <=>LCD app note            01/01/70 00:00      
            JTAG interface            01/01/70 00:00      
            darn            01/01/70 00:00      
               Xilinx CPLD applications handbook            01/01/70 00:00      
   Mahmood, stick with the recommended circuit            01/01/70 00:00      
      Recommended circuit            01/01/70 00:00      
         I would be really careful ...            01/01/70 00:00      
            Thanks Richard            01/01/70 00:00      
               don't be distracted by the unnecessary parts            01/01/70 00:00      
                  Xilinx Jtag for Altera            01/01/70 00:00      
                     How about Altera JTAG for ALTERA            01/01/70 00:00      

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