Thanks Jez,
I downloaded the App. Note. The maximum Sample rate is determined by this formula :
ADCSR = fClk/(2(MSBI+1) x (Fmst + 1) x (MSBI+1)) samples/second
I couldn't find anything about what is Fmst in the document.

AFAIK Delta-Sigma ADCs are not much fast.Can somebody confirm this ?
This way, Also I'll need to build a Sample/Hold circuit by Op-Amps (I didn't found one available locally when i was searching sometimes ago).

I asked in the electronic market here for the smallest CPLD and they introduced Altera MAX7000 family like EPM7032 and EPM7064.
Since I am not much familiar with PLDs I would be appreciated if you could help me by telling me would this family suffice my requirements.

Here is what am I expecting the CPLD to do for me :

- Have 2 counters each hopefully up to 24 Bits (Used for addressing the Read/Write Pointer)

- Be able to read in less than 50ns intervals (20 MHz)

- ability to output 500 to 40,000 kHz Clock (Used for the ADC Clock)

- Some small logic which manage the trigger function (start retrieving data when X=1 and stop after e.g. 1024 steps)

It would be better if it could implement these :
RS232 / USB / Parallel PC interface.
MMC (SPI) Interface for Data Acquisition (Log the samples in a mass storage device for further processing).

I was interested in using GALs , but I read they can't implement an internal counter and this lead me to leave them alone.

Farshid