Might be to have a look at xilinx app note 155 here
http://www.xilinx.com/xlnx/xweb...nguageID=1

Which shows how you can use some programable logic to produce an adc,doesn't have to use a spartan obviously, but it might save on parts count and input capacitance problems as you are going to have to put the sampled data into some sram prior to it being processed and displayed so why not incorporate that function into the same device which actualy produces the samples?
With Many FPGA's incorporating large amounts of on board ram the design is greatly simplified,you could even use dual port ram in the fpga to buffer the samples from the adc before feeding them to your processor stage.