Transistors are cheap, and draws a minimum of power, when stepping down on geometry sizes.

So it doesn't take much to create a two-bank code memory - each bank 16-bit wide.

Then a single 16-bit read from one bank handles an aligned 2-byte instruction in a single read.

And two 16-bit reads with instant merge of middle bytes handles an unaligned 2-byte instruction in a single read.

So a one-clocker could manage to always fetch 16-bit data (odd or even align) without use of any prefetch.

This technology was used in memory controllers for early 32-bit processors before the processors could get huge data and code caches - the user had to add memory in two or four memory banks but got lots of extra speeds from their workstation or server-class machines.

And the advantage here is that it only adds ns time to each access, but still gives constant-time accesses without the variation you get with caches and pipelines - there are no cache misses or pipeline restarts.

This technique is used on a number of ARM chips to get 64-bit or 128-bit access to the code memory.