| ??? 12/08/11 19:11 Read: times |
#185038 - A typical op Responding to: ???'s previous message |
Richard Erlacher said:
Do you mean that the part takes two cycles to execute a "single-cycle" instruction, or do you mean that many instructions are "two-cycle" instructions anyway? Some examples: 8051 AT89LPxxxx STC12C5Axx ADD A,Rn 12 1 1 ADD A,direct 12 2 1 DEC direct 12 2 1 MUL AB 48 2 4 ORL direct,#data 24 3 2 LCALL addr16 24 4 2 I presume that SiLabs are also not an automatic 12 to 1 correspondence. The best feature is the double buffered TX, RX on the SPI, so your SPI slave can run without any gaps. This seems to be a good feature. Have you pressed the rate limit on the SPI? I wonder how fast it can actually run. It will go at F_CPU/2. e.g. 10Mbits/s @ 20MHz F_CPU. The Slave is max F_CPU/4. Note that any of these speeds need polling. You struggle to get interrupts running that fast. All the same, a Slave implemented with this chip can emulate a real hardware chip. The STC chips can do SPI at F_CPU/4. e.g. 8.75Mbits/s @ 35MHz. Unfortunately they are not double-buffered on the TX. Both families can do push-pull output. Quite honestly, I would be suspicious of quasi output at high speed. Somewhere they suggest the odd NOP between toggling port pins. David. |
