I was surprised by the two-bytes in 1 cycle. And especially a CALL or RET in 2 cycles.

The Atmel timings seemed more intuitive.

I ordered on 6 Dec, so I might see the chips around 16 Dec if China Mail works ok.

I have a healthy scepticism, so I will time those ops myself. Mind you, data sheets are normally accurate on this sort of detail.

I can only assume that there is a pipelined fetch at all times. Whatever you do, a JMP or branch will upset any pipeline. Unless you maintain two pipelines (branch / no-branch).

Presumably all these speed techniques have been developed by the Intel / AMD wars. So a clever Chinese chip designer can add the extra logic to the simple 8051 core.

Personally, I think that a controller's peripherals are the selling point. So what, if they can process quickly! You want the I2C, SPI or whatever to be handled by the hardware. If you put an 8-bit core with typical ARM peripherals, you would be quite happy.

David.