The idea was that, If the VDD monitor has nothing to do with POR, then atleat the POR time should be equal to typical VDD ramp time!! ie: assuming the start of the VDD ramp and the reset pulse coincided. But then reset pulse always starts at a later point, I suppose.
The "supply monitor" will issue a reset at some voltage too low for the processor to do anything and keep it till Vdd is at a safe value. I have no idea what the "POR" does, it seems superflous to me. THUS at power on you will have (ignoring the "POR") a reset till Vdd is safe. If the "POR" does something it can not reduce the reset generated by the "supply monitor".

On the contrary, I wanted a longer reset!! If I have a 150 ms reset pulse, then may be I can handle a 150 ms VDD ramp. But then if the oscilator doesn't start at all with that ramp time, then 150 ms reset won't help. But then again, I assume that the oscilator starts up before the POR reset point. If oscillator itself hasn't started up, then even a long POR can't do anything.
The reset from the supply monitor will be there till Vdd reaches a safe value.

I turned off the VDD monitor just for experimenting - to see what happens when the voltage goes below 2.7 volts, which is the VRST point.
turn the monitor on in hardware and monitor !reset while the supply ramp up.

The above makes me think: you DO have the monen pin connected I hope, only enabling the supply monitor in software is erroneous (except in cases so unique that I can not think of one)


Just a small question to Kaai. What do you say that MAX1232 doesn't work well with active-low reset chips? An active low is an active low isn't it?
Kai is right (the MAX1232 will NOT work [with 3v3 chips]) and wrong (the MAX1232 has a !reset output) you need a supervisor that is intended for 3V3 chips.

Erik

PS: all the negaitves about the SILabs "low level" people filling you with BS is by no means a unique SILabs feature, the same is true for almost any other supplier.