the datasheet, POR is shown separated from VDD monitor. When we contacted Silabs, they advised us to go for an external sup chip or RC reset, if the VDD ramp time is 1 ms plus.
if the VDD monitor holds the chip in reset WGASA about the "POR"

Again, the question is, how long is the reset pulse when you use the internal POR.
if you care about this (as in is it 200 or 500 ms) your design is faulty. NO ill effect should come from an extended reset, e.g. what would happen during a 2 sec brownout?.

I did try to simulate slow VDD rise time using a variable supply.However slow I vary the VDD, the chip cranks up at 2.52 volts and works properly.
You have just proven that the Vdd monitor works

VDD monitoring was disabled in the code while doing this experiment.
which it never should be except if you have an external reset.

AGAIN
I have 10thousands of boards working with the SILabs reset and a pullup resistor with no problems, most of the SILabs people do not even have an inking of understanding of how their chips work. Try to get through to Brent at SILabs with your questions and you have a good chance of an intelligent answer. Maybe the people at MCUapps (link at the SILabs forum http://www.cygnal.org/scripts/U...tion=intro ) will know what actually happens, sometimes they do. Thay will definitely be better than your "european contact" that filled you with bullshit.

Erik

WGASA: http://www.netfunny.com/rhf/jokes...wgasa.html