We have been in contact with Silabs Europe. They have cautioned me against using the inbuilt POR. In built POR has no supervisor while the chip starts up, we were informed. (Even though the manual says the reet pin will be held low till VDD reaches VRST ie 2.7V, in the block diagram, they have separated VDD monitor and POR. We need to refer to the block diagram and not the confusing text below that). The VDD rise time required for Silabs is 1ms, and if the rise time is more than that, they recommend
The risetime has nothing to do with reset ... unless you put a capacitor on the reset pin.
HOWEVER, the risetime has something to do with whether the oscillator starts.

If you look at the schematic, you will see you have been fed a load of bullshit, a "supply monitor" is NOT risetime dependent. a "supply monitor" will reset or not depending on the supply.

Erik