I am using 340. Erik had explained that the cap is to be removed. The issue is 1)The datasheet say that the RST is held in reset state till the VDD reaches the VRST level. This implies VDD monitoring for POR, the way supervisory chips do. But in the blockdiagram in the previous page of the datasheet, POR is shown separated from VDD monitor. When we contacted Silabs, they advised us to go for an external sup chip or RC reset, if the VDD ramp time is 1 ms plus. Again, the question is, how long is the reset pulse when you use the internal POR. We had asked for details of the same, and are waiting for a reply. They had also clearly stated that there is absolutely no VDD monitoring during POR stage.

I did try to simulate slow VDD rise time using a variable supply.However slow I vary the VDD, the chip cranks up at 2.52 volts and works properly. Repeated the experiment many times. We had a mail from Silabs about this danger zone - 2.5 to 2.7 - where flash corruption is a serious possibility, if any flash read/write is attempted. When I reduced the voltage slowly, the chip kept working till 1.95 volts. Below 1.95, it hanged. VDD monitoring was disabled in the code while doing this experiment.