if the VDD monitor holds the chip in reset WGASA about the "POR"

The idea was that, If the VDD monitor has nothing to do with POR, then atleat the POR time should be equal to typical VDD ramp time!! ie: assuming the start of the VDD ramp and the reset pulse coincided. But then reset pulse always starts at a later point, I suppose. Again, the assumption is that, this reset pulse resets everything that needs to be reset, or rather, this reset pulse delays everything that should be started up at a safer VDD point, to a later point!!

Again, the question is, how long is the reset pulse when you use the internal POR.
if you care about this (as in is it 200 or 500 ms) your design is faulty. NO ill effect should come from an extended reset, e.g. what would happen during a 2 sec brownout?.

On the contrary, I wanted a longer reset!! If I have a 150 ms reset pulse, then may be I can handle a 150 ms VDD ramp. But then if the oscilator doesn't start at all with that ramp time, then 150 ms reset won't help. But then again, I assume that the oscilator starts up before the POR reset point. If oscillator itself hasn't started up, then even a long POR can't do anything.

I did try to simulate slow VDD rise time using a variable supply.However slow I vary the VDD, the chip cranks up at 2.52 volts and works properly.
You have just proven that the Vdd monitor works

VDD monitoring was disabled in the code while doing this experiment.
which it never should be except if you have an external reset.

That is what I said aloud when I found it starting up properly at 2.52 volts. But then when I received the email from the chip manufacturer himself confirming that there is no VDD connection to the POR, then I was disappointed. I turned off the VDD monitor just for experimenting - to see what happens when the voltage goes below 2.7 volts, which is the VRST point.

Just a small question to Kaai. What do you say that MAX1232 doesn't work well with active-low reset chips? An active low is an active low isn't it?


Raj Nambiar