| ??? 04/09/07 20:41 Read: times |
#136878 - FPGA-based processors Responding to: ???'s previous message |
Jan Waclawek said:
I am not much of FPGA/CPLD, but I cooperate with my colleague who just squeezed a design from two big CPLDs into a single small FPGA, but had a lot of #$%^ing around... His concern was mainly of the timing and troubles with wide combinatorial logic (adders and decoders and bus-wide multiplexers). Guess it all depends on what the design was doing, and what FPGA he was using. I remember fighting to get a VME design to meet the 80 MHz timespec in an XC4013E back in the day. Right now, I'm doing a Spartan 3E thing and I've got no problem meeting 66 MHz timing with ns to spare. One side of a dual-port runs at 133 MHz, too, without issues (clock doubling using the DCM). I can't imagine that it'd be difficult meeting, say, a 50 MHz clock requirement for an 8051 core in a 3E. -a |
