I am not much of FPGA/CPLD, but I cooperate with my colleague who just squeezed a design from two big CPLDs into a single small FPGA, but had a lot of #$%^ing around... His concern was mainly of the timing and troubles with wide combinatorial logic (adders and decoders and bus-wide multiplexers).

And, a processor is a mixture of sequential and combinatorial logic...

Now I know there are various architectures of FPGAs around and some might be better suited than the others, but, generally, for basic playing-with-things-around, wouldn't it be better to build it up from some combination of both?

Jan Waclawek