Jan,

Moving from discrete SSI/MSI logic to a CPLD, even a big one, is quite straightforward via schematic entry. HDL is also a decent way to do this, but making the same transistion to FPGA generally leads to disappointment.

FPGA's have logic cells based on lookup tables. Those lookup tables are loaded at boot time with all the possible values that can be produced by the logic being emmulated by that lookup table. The logic cell can be thought of as an SRAM with feedback. The LUT's limitation lies in that each input to the logic array it represents doubles its size. Most FPGA manufacturers have concluded that 4 inputs to a lookup table is probably all that's necessary. That means that you have to combine two lookup tables, hence, logic cells, in order to generate a wider gate, say, of 8 inputs, and four in order to generate an 8-input gate, and that process adds timing delays and also discards as useless all the other features, e.g, adders, fast-carry chain components, etc (counted as gates by the marketeers) in each of the concatenated LUT's. Sorting out the best implementation in a given FPGA can be quite a bit of work, though the result can be quite good. YMMV, however.

In a typical CPLD, there are large gates and a product-term sharing array. These feed a unltiplexer and a flipflop, as well as some buffers, any/all of which you can either use or not, but, as in the FPGA, if you use the gate but not the flipflop or tristate buffer, etc, it's gone despite the fact you didn't use it. The timing and pinout are not impacted, as that's generally considered to be fixed, as the signals have to propagate through the product term sharing array, the local product term and sum-term array, and the steering muxes, so the only impact on timing is whether the output is combinatorial or registered. That makes everything simpler and, consequently, easier and quicker. It doesn't make it better, though.

In short, with an FPGA, which offers, or at least seems to offer, much more in the way of resources, there's a lot of work involved in deciding WHICH of the many flipflop-bearing logic cells you use, as it impacts timing and that can impact pinout. If you know you need lots of wide gates and that they need to be fast, you'd best study the timing very carefully before deciding on an FPGA. With a CPLD, it's much less trouble.

If you're willing to do the work, an FPGA is a very good platform for a processor, or even a microcontroller, provided you can put all the peripheral functions you need in there. Gate counts are provided by marketeers, not engineers. I once had an FPGA mfg's sales person tell me that a D flipflop consisted of 14 gates, though I'd always thought of them as a half-dozen. Of course, he thought a 3-input gate was three two-input gates.

The key to understanding this programmable logic is to begin with "FPGA's are logic-poor, while CPLD's are register-poor." That is, of course, subject to interpretation, but, generally, it's quite true. The devil's in the details, and, with FPGA's, there are a lot of them. That's probably where your coleague is finding his frustration. AFAIK, the best results, both in performance and in utilization, are still attained by hand-routing by an experienced hand. Relying on the FPGA development software alone is a guarantee of late nights, increased aspirin and antacid consumption, not to mention an elevated need for sprirituous beverages.

RE