| ??? 10/03/06 22:04 Read: times |
#125776 - Hi David Responding to: ???'s previous message |
David Brown said:
true, the OUTPUT from the f/f will have a 50% duty cycle. But, if you would look in the fairchild datasheet posted above, you'll see that CMOS only draws significant current while switching; not while holding an output steady.
I'd wager the switching is done within nS (probably quicker actually) of the clock edge. The rest of the time it is just holding the output. As the frequency increases, the switching time (nS) stays the same, but it switches more often. If you can't see how that would change the duty cycle at the transistor level, and hence increase power draw... well... I don't know how else to say it. Regards, -Dave Hi David, Thanks for your input, You are quite correct that power is dissipated when we go 0..1 or 1...0, assuming good digital design is ahered to(we will perhaps look into a single ttl gate at some later time), a class c rf amplifier is supposedly 100% efficient but you only get about 75% in practice, 25% of the power is indeed lossed in the transistor switching, but then the transistor does not have infinity switching speed does it? which is why our efficiency drops from 100% to 75%(finite switching speeds). Please remember that we are not talking about circuit efficiencies on this thred, we are trying to find out why electrical frequencies are not dependent on power. http://en.wikipedia.org/wiki/Root_mean_square Best Regards Darren |
