true, the OUTPUT from the f/f will have a 50% duty cycle. But, if you would look in the fairchild datasheet posted above, you'll see that CMOS only draws significant current while switching; not while holding an output steady.

I'd wager the switching is done within nS (probably quicker actually) of the clock edge. The rest of the time it is just holding the output. As the frequency increases, the switching time (nS) stays the same, but it switches more often.

If you can't see how that would change the duty cycle at the transistor level, and hence increase power draw... well... I don't know how else to say it.

Regards,
-Dave