| ??? 08/25/10 15:59 Read: times |
#178311 - FPGA pin swapping Responding to: ???'s previous message |
Richard Erlacher said:
... but with FPGA's a pin swap can affect timing. That's why you wrote, in a previous post, that it's important which logic blocks contain which signals. That was certainly true for ancient parts, but for anything modern -- say, newer than the original Spartan and Virtex parts -- that's no longer the case. The devices have plenty of routing resources and timing is rarely degraded based on the location of the logic in the device. We NEVER worry about timing when assigning pins. It's just not necessary, even when dealing with high-speed (240 MHz DDR) memories and Camera Link serializer running at 280 MHz and internal logic running that fast. You get bitten on the ass by the various pin-assignment rules -- can't put LVDS outputs on these pins, that pin has a fast path to a DCM but that DCM has to be in this half of the chip, etc etc. -a |
