| ??? 08/24/10 16:31 Read: times |
#178284 - per-design CPLD/FPGA symbols Responding to: ???'s previous message |
Richard Erlacher said:
Since the library management is so stupidly done, I have to create a new symbol for nearly every part newer than 1990 and many that are older than that, and, as you know, programmable parts can have lots of pins ... <sigh> ... Now, if I have the same package, I still have to attach it to the schematic symbol. Since my programmables are treated as a specific device, with signal names relevant to the application, it's often in a package that I've already ensured is suitable, but ... since it has different signals on different pins, a new symbol is needed, and, therefore, a new footprint is needed as well. Sometimes I can cut and paste, but that, IIRC, doesn't always work. Oh, so you've fallen into the trap of creating an FPGA/CPLD symbol specific to each design? That can possibly work for 32-macrocell CPLDs but it's a major FAIL with even moderate-sized FPGAs. Why? The layout guy needs the freedom to swap pins (within specified constraints). If you've pre-assigned the pins and built a symbol around those assignments, you can't swap pins without editing the symbol first. And that's a non-starter. Our FPGA library has one multi-part symbol for each FPGA, and each symbol of course depends on package. The symbols are generally organized into the configuration/power section, and one subsymbol for each I/O bank. The I/O bank subsymbols also include the power pins for that bank, so you can look at the schematic and go, "ah, Bank 5 is 2.5V and Bank 6 is 1.8V." Now, understand that I normally don't involve myself in PCB production, and the guy who chooses the part based on price might be 5k miles away, and the guy doing the layout may be, as well. I like the approach that OrCAD uses, i.e. assigning the package when the device symbol is entered. Yes, you can make an error, but it's no different saying it's a 208PQFP20 on the schematic than saying it's an XC2S200PQFP when the schematic symbol is instantiated. If you call up the TQFP144, it's wrong. The procurement guy certainly doesn't like using differently packaged versions of the same part, but the layout guy certainly doesn't like using the 208PQFP where the 144TQFP would fit better. I prefer to let them work that out. The problem for me is that the layout editor demands that I modify the schematic symbol file for every identical programmable device just because I want to have the nets named so some human can understand who's who and what's what. The reason, of course, is that, sometimes, I'm that human. Regardless of who does the layout or who buys the parts -- we choose package sizes based on I/O requirements. If I only need 100 I/O (meaning it'll work in the 144-pin QFP) then I won't specify the 208-pin package. No need to involve the layout or purchasing person in this! Similarly, if a design requires a lot of logic, you might be forced into a larger package simply because the device with more logic isn't available in the smaller package. (Think Spartan 3AN-50 in the QFP vs 3AN-200 in FBGA256. Unfortunately no package-compatible upsizing here.) Again, this is a design decision, and the layout and purchasing folks' input/desire is irrelevant. Richard said:
Me said:
As for the CPLD (or FPGA) pinout, I absolutely DO care about this, as it's more than a simple back-annotation issue. You must make sure that your clocks are on the special clock input pins. With FPGAs that have multiple banks with different rails, you have to make sure that all of the 3.3V outputs are on a bank with a 3.3V rail, and all of the 2.5V outputs are on a 2.5V rail. And you have to make sure that LVDS outputs are NOT on pins called "LC" because they don't have LVDS outputs. And so on. I give the layout guy a list of layout rules for each design, indicating which signals can go in which banks, which cannot be swapped at all, and so forth. And before the board is released for fab, the FPGA tools are run on it to ensure that the chosen pins actually work.
-a This last bit is something for which no provision was made in bEAGLE, or, for that matte rin most other schematic/layout software, but which is a simple housekeeping matter. Yes, it's drudgery, and yes, it's error prone, but it's part of the job. Altium Designer does have some magic way of integrating FPGA designs into the layout as well as actually updating symbols with actual FPGA signal names. It's just that it's difficult to use and we don't see the point of tying up a PCB layout license to do FPGA stuff that's better done in its own environment. Aside: Altium Designer was a product that kept creeping up in price, and the increases in price were "justified" (in Altium's mind) because they added features like a VHDL simulation tool (which bombs on basic language constructs) and synthesizer and an 8051 compiler and all sorts of stuff that a PCB layout person doesn't need and doesn't want. What's worse is that they didn't offer an a-la carte option, where you could buy just PCB layout and schematic and leave the microcontroller and FPGA stuff out. And at some point they must've looked at their numbers and realized that nobody was upgrading to newer versions and nobody was buying new licenses because they were charging $15k per seat for stuff nobody wanted. Then they dropped the price of layout and schematic to something like $3500, which is in the realm of reality for stuff not called Mentor Board Station. =-a |
