...mainly in the "front end" ... i.e. the schematic capture and library portion of the software. It does the middle of the job, after schematic entry and package outline creation pretty well, but quits before the really important part of the autoroute, leaving a considerable amount of manual cleanup to be done.
[EDIT] (Erik is right ... this ought to be cleared up!) this refers, of course, to bEAGLE, from the poorer portion of which the subject software, Designspark ( http://www.designspark.com/pcb ), allows one to import. My concern is that some misguided people would make their situation worse by doing that, as I really can't imagine any functioning software that would do that part of the job any worse than bEAGLE does it.[/EDIT]

My issue with the first portion of the work, aside from the utterly terrible library management, is that you must provide a specific component outline (footprint) for each symbol in your schematic, which, first of all, means that if you have to adapt your footprint to the specifics of a particular board house, you then have to alter all of the parts in your repertoire that use that package outline, else you'll never again know which ones are "correct" and which are not. Moreover, it's poorly suited to team usage, since, generally speaking, the circuit designer doesn't care about the component outline as much as the guy handling the mechanical (including airflow) factors and the guy actually doing the board layout.

Unfortunately, a new library member has to be produced, including a new footprint, for each schematic in which the package is changed. A "real" software package would allow one to refer to a global package outline library so that the package outline would only have to be entered once, and corrected only once, rather than 1500 times because you now buy the TQFP rather than the PLCC. My own experience with bEAGLE required me to change dozens of components in TQFP and PQFP packages because someone entered the package outline incorrectly, leaving far too much pad under the component, where it couldn't be inspected properly, therefore requiring that each and every component in TQFP208 (consider how many pads have to be changed ... manually ...in order to effect that change) in a series of boards with a dozen of them on it.

From where I sit, the circuit designer chooses the device, but it's up to the purchasing, mechanical, and layout guys to choose the package. It works fine if I'm wearing all of these hats, but if someone is waiting for a schematic and I first have to create the package outlines for components I can't find in the libraries, I find it burdensome, since I, as the circuit designer, don't care about the package or, generally, about the pinout of a CPLD where it's just a back-annotation matter. I do care about the two-hour search for the component and the hour it takes to create a new "component" despite the fact there are already ten versions of the same device in the libraries. Sadly, it's seldom possible to use copy-and-paste because the schematic needs the signal names to match the device signal assignments.

It is, of course, possible to perform the processes ahead of routing, i.e. up through netlist generation in another schematic capture package, and I've done that using the Old DOS OrCAD software. This cuts out 90% of the schematic entry task, but it still requires that library components exist, and those require that a device-specific component outline be present.

Over all, I'd say that importing, into ANY routing package that has a local schematic entry tool, using bEAGLE to handle that part of the task that bEAGLE handles least well is not an advantage, aside from the few instances in which the schematic, and probably the board, already exist.

Note that I'm contrasting this dog, a freebie for small two-layer boards, with the very fast, very efficient, much more complete, and equally free Old-DOS-OrCAD stuff, with a schematic entry package that doesn't require a new footprint for every new component, a digital simulator ... yes, a bit primitive ... a PLD package, and an autorouter/PCB-Editor that handles large boards in up to 16 layers.

RE