??? 08/25/10 04:56 Read: times |
#178301 - You're right on target Responding to: ???'s previous message |
As you've said, you have to pin-swap, etc, where possible. Since I sell the IP, however, I do want the CPLD's and FPGA's to be the place where the signals are defined. In those cases where I provide the devices, complete with labels, I have to have my own guy do the layout so that pin swapping where necessary and practical is possible. That's seldom the case with CPLD's, but with FPGA's a pin swap can affect timing. That's why you wrote, in a previous post, that it's important which logic blocks contain which signals.
That, also, is another reason why the bEAGLE stuff is such rubbish. When I have to change the pinout, I always have to back-annotate the schematic, but I dislike very much having to change the package spec as well as the symbol. It's much smarter to have the signals associated with the schematic and not also with the library symbol. If I pin-swap an address or data pair on a RAM, for example, which has little consequence of any sort, I simply assign the signals on the schematic. It's simple in the old OrCAD package, simply because I have to assign the package once and be done with it. If I change from a 0.600" (32DIP600) to a "skinny" dip, however, I have to reassign the package association to the library's 32DIP300 on the schematic, and the netlister picks it up as the data is transferred to the layout tool. In bEAGLE ... well, it's a different story. The result is that the board may ultimately contain several different versions of any one package, owing to the fact that each schematic symbol has to be associated with a package outline graphic, even though they could, and should, all be the same. Yes, proper management would ensure that they are, but over time things get changed, and in the interest of expediency, people "forget" to make it global. As I've said, the process is adequate for a one-man shop, but if you have a team, the process breaks down because the layout guy doesn't have to sign the schematic, and the circuit designer doesn't, in all cases, have to take ownership of the layout. RE |