VHDL allows greater levels of design abstraction than verilog, but in terms of ease of use they are like any other language in that if you use them everyday you soon get used to them.
I recently inherited a design which was written in AHDL which is a mickey mouse Altera language and I had to convert it to VHDL before it was usable which wasn't much fun.
I have seen verilog used in europe when the director of engineering was American.