I know both language, having had to use them at different jobs. Both languages are equally supported by the major FPGA synthesis and simulation vendors.

First and foremost: if someone says, "VHDL is like Ada and Verilog is like C, so if you know C, Verilog is easy," you are to whack them upside the head with a Louisville Slugger (use ash; maple shatters) until they realize the inanity of their statement. And then whack them a couple more times, just to be sure.

Verilog's proponents proclaim its brevity makes it superior to VHDL's verbosity. That's because VHDL is a strongly-typed language. Verilog has no types. Doing any sort of math operations in Verilog is difficult because of that. Verilog has non-obvious sign-extension and truncation rules, which basically allow you to have the left-hand-side of an assignment have a vector of a different size than anything on the right-hand-side, and you get ... something. Verilog's operators use the same symbols as C but beware. Verilog allows you to mix blocking and non-blocking assignments in the same always block. Engineers who do this tend to find that their designs fail at the worst possible moment.

Previous revisions of Verilog forced you to declare port signals three times: once in the port list itself, once again in the body of the module to indicate whether the ports are in, out or inout, and finally a third time if any of them are reg types. Verilog-2001 introduced a streamlined module port definition that rolled all of that up into one, but many people (and lots of example code from vendors) still uses the obsolete style.

VHDL makes you consider the type of everything. You can't just add one bit vector to another, everything in an assignment has to be of the same type and have the same length. Conversion functions and attributes (something Verilog doesn't have) simplify these operations. Integers can be given ranges and if you attempt to assign something outside of the range, the simulator will complain (instead of your customers). You can declare an enumerated type for state-machine states, declare a signal of that type for the state register, and you don't have to worry about the width of that register or the specific bit-vector pattern assigned to it. So if you add another state, you just add it to the enumeration definition and go. Verilog makes you `define each state and it gets annoying quickly.

VHDL allows for both blocking and non-blocking assignments, but unlike Verilog, variables can only do blocking assignments and signals can only do non-blocking. Furthermore, variables can only be used in a process, restricting their scope so you don't find yourself assigning to variables all over the place.

Verilog's notions of functions and tasks is somewhat simpler and more intuitive than how VHDL deals with them. VHDL's scoping rules can get in the way of reasonable function and procedures.

Recent Verilog includes ways of doing vector slices that seem peculiar to me (possibly because of their brevity). VHDL has had bit slices in the language since the beginning, and their implementation is straightforward.


I'm sure I can think of a lot more.

But here's the kicker: emacs has the most-excellent vhdl-mode, which goes a long way towards mitigating VHDL's verbosity. Type pr<tab> and voila, you have the start of a process template and you can either have defaults for things (like clocks, reset style etc) or fill in the blanks as you go along. And all of the templates are much easier to use than any other editor I've used.

So, yes, I prefer VHDL. YMMV.

-a