I see more people starting with VHDL than with Verilog, but for other reasons.

Verilog was "ready for prime-time" somewhat before VHDL, but VHDL was "free" (as in beer) before Verilog (IIRC). This influenced many companies to buy into Verilog, which was very costly, so they could get under way, while numerous educational institutions decided on VHDL because it was not so costly and because it was headed in more "interesting" directions on the world scene. Yes, VHDL is a bit more demanding of the beginner, but it doesn't tempt the beginner to rely on knowledge of some programming language or other as much. Many confusing questions regarding syntax have originated with one's knowledge of 'C'. It's obvious that this would happen in a language closely resembling 'C' at first glance.

VHDL and Verilog are, once learned, both effective tools for describing logic.
The trick, as always, is learning them before trying to use them for serious work.

RE