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04/13/11 17:55
Modified:
  04/13/11 18:41

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#181868 - Man, someone rubbed you wrong
Responding to: ???'s previous message
Andy Peters said:
Most people start with the language that their company has chosen.

Highly unlikely. They learn what they should have back in college which is based solely on the professor teaching the class.
Andy Peters said:
If you say, "a beginner will start with Verilog because it is more C-like," please re-read my first post on this subject. The last thing the world needs is software guys trying to translate their sequential C code into an HDL.

I did not say that. In fact, you've been rubbed wrong so many times by this argument that this is the only argument you know. Take a look at the link I posted previously.
Link Provided said:
Starting with zero knowledge of either language, Verilog is probably the easiest to grasp and understand. This assumes the Verilog compiler directive language for simulation and the PLI language is not included. If these languages are included they can be looked upon as two additional languages that need to be learned. VHDL may seem less intuitive at first for two primary reasons. First, it is very strongly typed; a feature that makes it robust and powerful for the advanced user after a longer learning phase. Second, there are many ways to model the same circuit, specially those with large hierarchical structures.


Andy Peters said:
The synthesis component of the FPGA tools is actually the simple part. The rest of it? Yeesh.

For the guy writing the VHDL or Verilog, yes. You do not have to worry about it! The guy who wrote the development package? That was my point.

Andy Peters said:
What does that mean? Are you saying that the Xilinx architecture is more suited to synthesis than, say, Altera, or are you saying that their synthesis tool is "better?"

The synthesis tool is better, but you also have to incorporate their hardware along with that view. I guess it could be similar to comparing IAR to Keil. The compilers are different. Just like Altera's synthesis tool is different from Xilinx, but they are chip specific. So, you cannot really isolate hardware from the equation. I'm not telling you that you've made the wrong decision to go with Altera. For instance, I like the FPGAs Lattice provides, but I do not like the development software. I like the development software Xilinx provides, but their FPGA's can be a little overkill. I really do wish that there was an open source development software that worked with all FPGAs (dreaming).

Andy Peters said:
Xilinx (and Altera, and Actel, and Lattice) offers free (as in beer) versions of their tools. The free versions use the same synthesis engine (not crippled), the same place and route tools (also not crippled) as the paid-for version; the main difference is that the largest devices are not supported by the free version. (In the Xilinx world, you do have to pay for ChipScope and the EDK. But the main tools are free.)

For the purposes of those books above, Xilinx has a free Webpack ISE that can be used to start learning right away, once the board and book have been had.


Altera, Lattice and Actel also have free tools and available low-cost development boards.


All very true, but my point was that if you really wanted to take advantage of the books written by that author that you would have to get the hardware specific to Xilinx. I have yet to see a substitute using that same style of book with Altera or any other FPGA provider. You could write a book?

List of 27 messages in thread
TopicAuthorDate
Verilog or VHDL?            01/01/70 00:00      
   maybe somewhat unrelated            01/01/70 00:00      
      How very true!            01/01/70 00:00      
   not so simple answer            01/01/70 00:00      
   Verilog is easier to learn            01/01/70 00:00      
      the holy war            01/01/70 00:00      
         Man, someone rubbed you wrong            01/01/70 00:00      
         It's not worth bloodshed            01/01/70 00:00      
   Thanks, more detail            01/01/70 00:00      
      PCIe in FPGA            01/01/70 00:00      
         PCIe hard endpoint            01/01/70 00:00      
            Job Requirements?            01/01/70 00:00      
               simple method            01/01/70 00:00      
               Regional?            01/01/70 00:00      
                  Well, Verilog was on the market first            01/01/70 00:00      
   In Europe            01/01/70 00:00      
      blah            01/01/70 00:00      
      Reference designs            01/01/70 00:00      
         and...            01/01/70 00:00      
   ELLA            01/01/70 00:00      
      Gee ... That's a new one to me ...            01/01/70 00:00      
         Note the dates            01/01/70 00:00      
            Yes ... VHDL was still pretty mysterious then ...            01/01/70 00:00      
            "widely used" should also be qualified            01/01/70 00:00      
               VHDL was also a Military/Industrial Complex product            01/01/70 00:00      
         productivity            01/01/70 00:00      
            I believe that's an implementation problem            01/01/70 00:00      

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